In a semiconductor integrated circuit device, particularly a DRAM (dynamic random access memory), it is very important to increase integration and make multilayer wirings microscopic. According to a first conventional approach, for example, disclosed in Laid-open Japanese Patent Application No. 06-120447 the DRAM design is structured to include two plugs, having a reverse trapezoidal cross section and with the bases thereof being smaller than the top, which are directly connected electrically to connect a diffused layer of a MOS transistor and a lower electrode of a capacitor (a storage node electrode) that consists of a polycrystal silicon, in a DRAM memory array portion.
In conventional, DRAMs, a storage capacitor is, typically, placed in a lower portion of a bit line or just above it, similarly to the case of the first conventional method, described above. In that case, however, one problem is that a focus margin in photolithography cannot cover a stage difference between a memory array portion and a peripheral circuit portions (an I/O control circuit portion and a decoder portion), posing limitations to microminiaturization. Further, in the case of fabricating an LSI chip containing a logic circuit, in addition to a memory array portion having a capacitor of a DRAM, etc., the above problem creates a major drawback.
Accordingly, there is proposed a structure in which a capacitor is formed above wiring layers for the purpose of eliminating the limitations on microminiaturization by reducing the stage difference described above. For example, according to a second conventional approach, for example, in Laid-open Japanese Patent Application No. 06-085187, a plug for connecting a diffused layer of a MOS transistor and a lower electrode of a capacitor are formed after wiring layers have been formed.
The first conventional art described above has the problem that because the cross section of the plugs is of reverse trapezoid shape with the sides not vertical and the top area large, the plugs occupy a large area and an area per memory cell increases. Although a polysilicon film is used as a lower electrode of a capacitor of the memory cell array portion, because smaller resistance is required for use as plugs of peripheral circuit portions and a logic circuit portion, a metallic film such as a tungsten film, etc. is usually used. Accordingly, the memory cell array portion, the peripheral circuit portions, and the logic circuit portion require that plugs made of mutually different materials be formed through processes different for each of them, increasing the number of process steps.
Thus, the conventional arts cannot solve three problems simultaneously: (1) making a memory array portion microscopic; (2) lowering the resistance of plugs of peripheral circuit portions and a logic circuit portion; and (3) lowering fabrication cost.
On the other hand, as with the second conventional art, in the case of forming a plug for connecting a diffused layer of a MOS transistor and a lower electrode of a capacitor after forming a wiring layer, although there are required the process to form holes with a large aspect ratio and the process to form plugs by padding the holes with a metallic film, the processes are technically difficult, making it difficult to obtain satisfactory results. Especially when the depth of a connection hole exceeds 1.0 .mu.m, the formation of the hole and the padding of a metallic film becomes very difficult, a yield decreases, and fabrication cost increases. This method requires a large alignment margin for layer alignment among multiple layers in photolithography performed to form connection holes, so that a unit memory cell area increases.